SMOS processes are utilized to increase transistor (MOSFET) performance by increasing the carrier mobility of silicon, thereby reducing resistance and power consumption and increasing drive current, frequency response and operating speed. Strained silicon is typically formed by growing a layer of silicon on a silicon germanium substrate or layer. Germanium can also be implanted, deposited, or otherwise provided to silicon layers to change the lattice structure of the silicon and increase carrier mobility.
The silicon germanium lattice associated with the germanium substrate is generally more widely spaced than a pure silicon lattice, with spacing becoming wider with a higher percentage of germanium. Because the silicon lattice aligns with the larger silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. Relaxed silicon has a conductive band that contains six equal valance bands. The application of tensile strength to the silicon causes four of the valance bands to increase in energy and two of the valance bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus, lower energy bands offer less resistance to electron flow.
In addition, electrons meet with less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1,000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon compared to relaxed silicon, providing an increase in mobility of 80 percent or more for electrons and 20 percent or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolt/centimeter. These factors are believed to enable device speed increase of 35 percent without further reduction of device size, or a 25 percent reduction in power consumption without reduction in performance.
High levels of germanium at the surface of a wafer can adversely affect the formation of silicide layers. In particular, high concentration of germanium in a top surface of a substrate can adversely affect the formation of silicide layers above the source and drain regions. The germanium concentration at the top surface can be exacerbated by the processing associated with source and drain regions and gate structure formation.
Silicidation of strained silicon or germanium containing layers can be difficult. For example, the presence of germanium in a silicon layer can cause germanosilicides to form during the silicidation process. Germanosilicides negatively impact the formation of a silicide region.
After pre-cleaning native oxides from a top surface of the wafer, a metal can be deposited. The metal layer can be reacted with the semiconductor surface of the wafer to form a metal silicide (MexSiy) region such as a titanium silicide layer, a nickel silicide layer, a cobalt silicide layer, etc. The pre-cleaning process can cause germanium contamination due to resputtering.
Thus, there is a need for an efficient process for forming silicide wafers on a wafer surface in an SMOS process. Further, there is a need for a system and a method which reduces germanium contamination of silicide regions. Even further, there is a need for a method of siliciding and a transistor architecture which avoids germanosilicides. Yet further, there is a need for a process which reduces the adverse effects of germanium on silicidation processes.